Fprox’s Substack

Fprox's Substack focuses on advancements and technical aspects of RISC-V, including its vector extension, cryptographic enhancements, and computer arithmetic. It covers implementation details, new profiles, programming techniques, and the addition of new instructions, emphasizing RISC-V's role in modern computing and its support for complex operations and machine learning.

RISC-V Architecture Computer Arithmetic Vector Processing Cryptography Programming with RISC-V Floating-Point Operations Software Development Tools Mathematical Libraries Machine Learning

The hottest Substack posts of Fprox’s Substack

And their main takeaways

RISC-V Compressed Instructions (part 1): C extension

0 implied HN points • 26 Dec 22
  1. RISC-V base instructions are 32-bit wide and follow a standard encoding pattern, making decoding easier
  2. RISC-V C extension introduces 16-bit wide compressed instructions for code size improvements
  3. Compressed instructions use reduced immediate ranges and register indices, providing code size reduction at the cost of expressiveness

RISC-V Vector Extension in a Nutshell (Part 3): mask & masked operations

0 implied HN points • 17 Aug 22
  1. Most operations in RVV 1.0 can be masked by providing an extra mask operand through v0.
  2. The mask size of a mask in RVV 1.0 is VLEN, even for the largest possible vector group.
  3. Specific instructions in RVV 1.0 can produce masks for non-mask operands, and there are operations on masks like standard bitwise logic and population count.

RISC-V Vector extension in a nutshell (Part 5.1): vector loads and store

0 implied HN points • 06 Sep 22
  1. RISC-V Vector extension defines different memory operation families like unit-strided load/store and strided load/store
  2. Effective element width for most loads and stores is determined by the opcode, not SEW
  3. RVV 1.0 introduces segmented loads and stores to transform AoS in memory to SoA in vector registers

Assisted assembly development for RISC-V RV32

0 implied HN points • 04 Sep 21
  1. ASMDE tool helps in assembly program development for RISC-V RV32 by automating register allocation
  2. Example program demonstrates how to implement a basic vector add routine using ASMDE template and main.c file
  3. ASMDE provides specific constructs like asmde macro and assembly variables to simplify assembly programming

Accelerating Erasure Coding with Bit Matrix Multiply

0 implied HN points • 12 May 19
  1. Erasure coding can be accelerated using Galois Field arithmetic.
  2. Multiplication by a constant can be achieved through vector by matrix multiplication.
  3. Parallelization can be used to implement multiple multiplications by the same constant simultaneously.
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Computing floating-point division from an accurate reciprocal [WiP]

0 implied HN points • 25 May 19
  1. The method computes floating-point division by utilizing an accurate reciprocal approximation.
  2. Special case management is crucial to ensure accurate results and avoid exceptions.
  3. Managing overflow and underflow is essential for precision during the computation.

RISC-V Vector Element Groups

0 implied HN points • 18 Jan 23
  1. RISC-V Vector extension introduces vector element groups to organize data in a new way for efficient processing.
  2. Element groups are defined by an element width and group size, allowing manipulation of multiple elements as a single entity.
  3. Support for element groups provides a unique approach to enhance vector processing capabilities without requiring major hardware changes.

On the quality of random

0 implied HN points • 18 Jun 18
  1. True Random Number Generators (TRNG) produce truly random numbers compared to deterministic generators.
  2. The quality of random number generators can be tested using NIST's suite of tests to ensure unpredictability.
  3. It's challenging to verify if a source is truly random, as no test can prove absolute randomness.

Support of half precision floating-point numbers in RISC-V ISA: Zfh and Zfhmin

0 implied HN points • 03 Nov 22
  1. RISC-V supports half precision floating-point numbers through extensions like Zfh and Zfhmin
  2. Zfh extension adds instructions for arithmetic operations, comparisons, conversions, and more for half precision values
  3. There are also vector extensions like Zvfh and Zvfhmin for half precision support in vector operations

RISC-V Vector Extension in a Nutshell (Part 4): permute operations

0 implied HN points • 20 Aug 22
  1. RISC-V Vector Extension offers various types of permutation operations to manipulate and re-organize data within vector registers.
  2. There are different types of permutation instructions like full permute, vector splat, vector slide, and vector compress, each serving different purposes.
  3. Permutation instructions are crucial for efficiently copying vector register files and implementing lookup tables.