Fprox’s Substack

Fprox's Substack focuses on advancements and technical aspects of RISC-V, including its vector extension, cryptographic enhancements, and computer arithmetic. It covers implementation details, new profiles, programming techniques, and the addition of new instructions, emphasizing RISC-V's role in modern computing and its support for complex operations and machine learning.

RISC-V Architecture Computer Arithmetic Vector Processing Cryptography Programming with RISC-V Floating-Point Operations Software Development Tools Mathematical Libraries Machine Learning

The hottest Substack posts of Fprox’s Substack

And their main takeaways

Implementing Softmax using RISC-V Vector

39 implied HN points • 12 Feb 24
🕹 Technology Programming Algorithms Computing Simulation Hardware
  1. Softmax is a non-linear normalization layer commonly used in neural networks to compute probabilities of multiple classes.
  2. When implementing Softmax, numerical stability is crucial due to exponential function's rapid growth, requiring clever techniques to prevent overflow.
  3. RISC-V Vector (RVV) can be used to efficiently implement complex functions like Softmax, with stable and accurate results compared to naive implementations.

Transposing a Matrix using RISC-V Vector

27 HN points • 09 Jan 24
🕹 Technology Programming Hardware Algorithms Benchmarking Software Development
  1. Transposing a matrix in linear algebra is a common operation to switch row-major and column-major layouts to optimize computations.
  2. Different techniques like strided vector operations and in-register methods can be used to efficiently transpose matrices using RISC-V Vector instructions.
  3. Implementations with segmented memory variants and vector strided operations can be more efficient in terms of retired instructions compared to in-register methods for matrix transpose.
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RISC-V vector crypto spec freeze update

19 implied HN points • 25 Jun 23
🕹 Technology Crypto Extensions Specifications Performance
  1. The RISC-V vector crypto specification has reached the frozen milestone after approval by the ARC and RVIA committee chairs.
  2. Changes include revised instructions for better integration, addition of new instructions like 'vgmul.vv', and splitting the Zvkb extension into Zvbb and Zvbc.
  3. The new Zvkt extension emphasizes data-independent timing for secure software implementations and the specification introduces meta-extensions for different cryptography suites and simplified illegal instruction conditions.

Adding a new RISC-V instruction (to LLVM)

19 implied HN points • 05 May 23
🕹 Technology Compiler Simulation
  1. Extending LLVM to support new RISC-V instructions involves modifying source files and declarations in LLVM's target description files
  2. Testing the generated binary involves building LLVM with RISC-V support, enabling experimental extensions, and linking the binary with the GNU toolchain
  3. This process allows programmers to utilize new RISC-V extensions and instructions efficiently

RISC-V Vector in a Nutshell

19 implied HN points • 03 Feb 23
  1. The series introduces RISC-V Vector Extensions
  2. Different articles cover arithmetic, masks, permute operations, and memory operations
  3. RVV defines vector register groups for efficient operations

RISC-V Vector extension in a nutshell (part 1)

19 implied HN points • 28 Jan 23
  1. RVV adds a new instruction set extension for the RISC-V ISA with 32 vector registers
  2. Parameters like vl, SEW, and LMUL affect how many elements are operated on and the size of vector groups
  3. RVV instructions can have optional mask operands to control which elements are modified

RISC-V Vector Programming in C with Intrinsics

3 HN points • 23 Nov 23
🕹 Technology Programming Hardware
  1. RISC-V Vector Programming can be done in C using RVV Intrinsics, providing a more modern and accessible approach than assembly programming.
  2. RVV Intrinsics are low-level functions exposed by the compiler that have a one-to-one mapping with corresponding RVV instructions, embedding vector configuration information.
  3. The RVV Intrinsic API offers a variety of intrinsics for different types, operations, and configurations, enabling efficient programming with RISC-V Vector instructions.

How to read a RISC-V Vector assembly instruction

19 implied HN points • 22 Nov 22
  1. The mnemonic describes the operation in a RISC-V Vector assembly instruction.
  2. Operand types impact how operations are performed, such as on vectors or scalars.
  3. Mask operands are used to determine active elements and behavior in RVV operations.

RISC-V support for BFloat16

3 HN points • 04 Sep 23
🕹 Technology Computer Science Hardware Programming Machine Learning Data processing
  1. Brain Float 16 (BFloat16) format provides a compromise between accuracy and cost suited for machine learning applications.
  2. RISC-V is introducing support for BFloat16 format through scalar and vector extensions to improve efficiency in machine learning tasks.
  3. The new BFloat16 extensions in RISC-V have passed Architecture Review and are designed to be fully IEEE-754 compliant for numerical reproducibility.

Zimop/Zcmop may-be-operations

2 HN points • 15 Oct 23
🕹 Technology Extensions
  1. When designing new instructions, ensuring compatibility with older implementations can be challenging.
  2. Zimop and Zcmop introduce placeholder instructions that can be leveraged for future functionalities.
  3. These extensions may not have immediate impact, but pave the way for implementing specific features like control flow integrity in the future.

RISC-V Profiles

5 HN points • 22 Mar 23
🕹 Technology Hardware Software Profiles Specifications Extensions
  1. RISC-V profiles consist of base ISA, mandatory, and optional extensions organized into families for specific modes.
  2. Allowing optional extensions in profiles promotes compatibility and testing of new features before mandating them.
  3. The concept of major and minor profile versions ensures a balanced evolution of profile families while allowing time for ecosystem adoption.

Adding a new RISC-V extension (to spike)

2 HN points • 14 Apr 23
🕹 Technology Coding Simulation Extensions Development Testing
  1. The post describes how to extend the RISC-V ISA simulator Spike to implement a new instruction for vector AES-128 encryption.
  2. It covers steps like adding the new opcode in riscv-opcodes, declaring the new instruction in riscv-isa-sim, and testing the program.
  3. The process involves modifying opcode header files, updating the simulator, and building a test program to implement and verify the new instruction.

Accelerating Erasure Coding with Bit Matrix Multiply

0 implied HN points • 12 May 19
  1. Erasure coding can be accelerated using Galois Field arithmetic.
  2. Multiplication by a constant can be achieved through vector by matrix multiplication.
  3. Parallelization can be used to implement multiple multiplications by the same constant simultaneously.

Computing floating-point division from an accurate reciprocal [WiP]

0 implied HN points • 25 May 19
  1. The method computes floating-point division by utilizing an accurate reciprocal approximation.
  2. Special case management is crucial to ensure accurate results and avoid exceptions.
  3. Managing overflow and underflow is essential for precision during the computation.

RISC-V Vector Element Groups

0 implied HN points • 18 Jan 23
  1. RISC-V Vector extension introduces vector element groups to organize data in a new way for efficient processing.
  2. Element groups are defined by an element width and group size, allowing manipulation of multiple elements as a single entity.
  3. Support for element groups provides a unique approach to enhance vector processing capabilities without requiring major hardware changes.

On the quality of random

0 implied HN points • 18 Jun 18
  1. True Random Number Generators (TRNG) produce truly random numbers compared to deterministic generators.
  2. The quality of random number generators can be tested using NIST's suite of tests to ensure unpredictability.
  3. It's challenging to verify if a source is truly random, as no test can prove absolute randomness.

Support of half precision floating-point numbers in RISC-V ISA: Zfh and Zfhmin

0 implied HN points • 03 Nov 22
  1. RISC-V supports half precision floating-point numbers through extensions like Zfh and Zfhmin
  2. Zfh extension adds instructions for arithmetic operations, comparisons, conversions, and more for half precision values
  3. There are also vector extensions like Zvfh and Zvfhmin for half precision support in vector operations

RISC-V Vector Extension in a Nutshell (Part 4): permute operations

0 implied HN points • 20 Aug 22
  1. RISC-V Vector Extension offers various types of permutation operations to manipulate and re-organize data within vector registers.
  2. There are different types of permutation instructions like full permute, vector splat, vector slide, and vector compress, each serving different purposes.
  3. Permutation instructions are crucial for efficiently copying vector register files and implementing lookup tables.

A brief history of open source libms (mathematical libraries)

0 implied HN points • 14 Mar 21
  1. C libm is a standard for mathematical functions with implementation details found in ISO standards.
  2. Various libm implementations exist, with origins from fdlibm and IBM's libultim.
  3. Libm is used as a basis for languages like C++ and has extensions for special mathematical functions.

Docker Power

0 implied HN points • 31 Dec 18
  1. Docker is a lightweight and elegant way to package and deploy applications.
  2. Docker is not a virtual machine system and is used for specific runtime applications.
  3. Using Docker is helpful for managing applications with complex dependencies.

Determining numerical bound for floating-point reciprocal overflow

0 implied HN points • 06 Aug 18
  1. The article discusses finding a numerical bound for floating-point reciprocal overflow.
  2. Important considerations include rounding modes and precision when evaluating the overflow bound.
  3. Through calculations and approximations, the study concludes key insights about overflow behavior in different rounding modes.

RISC-V Vector Extension in a Nutshell (Part 2): arithmetic operations

0 implied HN points • 13 Aug 22
  1. RISC-V Vector Extension Part 2 discusses arithmetic operations in RVV 1.0
  2. RVV 1.0 specifies various families of arithmetic and logic instructions for vector operations
  3. Instructions in RVV 1.0 can be masked and tuned by global parameters like vstart, vl/LMUL, and SEW

Testing metalibm from the demo Docker image

0 implied HN points • 19 Aug 19
  1. A Docker image with a demonstration version of metalibm allows testing basic commands.
  2. The Dockerfile used to build the image includes installing necessary packages and dependencies.
  3. Metalibm installation can be tested within the image using provided commands.

New instruction for Fast GCM multiplication

0 implied HN points • 30 Dec 17
  1. Galois Counter Mode (GCM) uses finite field multiplication for authentication
  2. Carry-less multiplication simplifies polynomial operations
  3. Implementing GCM multiplication efficiently can reduce costs by optimizing operations

Short note: consequence of arithmetic overflow

0 implied HN points • 03 Aug 16
  1. Pointer arithmetic in C can lead to security breaches if not carefully implemented.
  2. Arithmetic overflow must be considered, especially in sensitive scenarios like security.
  3. Be cautious with pointer arithmetic, especially with memory allocation sizes.

RISC-V Vector Cryptography Extension (2/2)

0 implied HN points • 20 Feb 23
🕹 Technology Cryptocurrency Hardware Security Software Encryption
  1. There are new instructions for hash functions like SHA-2 and SM3 in the RISC-V vector cryptography extension.
  2. The Zvkb extension includes instructions for bit manipulation like bit and byte reversal, vector rotations, and carry-less multiplication.
  3. The vector cryptography extensions have specific encodings within the opcode spaces, making them incompatible with certain future extensions.

RISC-V Vector Cryptography Extensions (1/2)

0 implied HN points • 12 Feb 23
  1. RISC-V is introducing a new vector cryptography extension with 22 new instructions dedicated to cryptography
  2. The extension includes ciphers like AES and SM4, each with specific instructions for encryption/decryption rounds
  3. The vector cryptography extension leverages vector element groups and supports various key sizes for encryption/decryption

RISC-V Compressed Instructions (part 2): Zc extensions

0 implied HN points • 14 Jan 23
  1. Zc* is a family of 6 extensions including Zcf, Zcd, Zca for enhanced code size.
  2. Zcb extension offers compressed loads/stores for smaller data sizes with limited register addressing.
  3. Zcmp introduces instructions like push, pop, and paired register moves to optimize function calls and returns.

Performance simulation of RISC-V vector extension using GEM5

0 implied HN points • 17 Jan 22
  1. The fork of gem5 called plct-gem5 is active and supports RVV 1.0, with a vector processing unit extension.
  2. To build gem5 for RISC-V, necessary external dependencies must be installed, and the build can be executed using specific commands.
  3. Although the fork for gem5 is still under development, it provides RVV support and vector processing unit extension.

Computing floating-point approximation of log(1+x)

0 implied HN points • 10 Mar 19
  1. log1p and log1pf functions approximate log(1+x) in standard math libraries
  2. Accurate polynomial approximation can be used for log(1+x) around 0
  3. Generic approximation of log(1+x) involves decomposition into mantissa and exponent

RISC-V Vector Register Groups

0 implied HN points • 29 Nov 22
  1. RISC-V Vector Extension uses vector register groups for efficient processing.
  2. Register groups can have different sizes like 1, 2, 4, or 8 registers.
  3. Register grouping can increase architectural constraints and impact register allocation.

RISC-V Register Files

0 implied HN points • 18 Oct 22
  1. RISC-V ISA defines multiple register files, including general purpose, floating-point, and vector register files.
  2. Each register file has specific characteristics like size and purpose, influencing how data moves between them.
  3. Having separate register files allows for more architectural registers without extending instruction encoding, optimized data storage, and efficient execution pipeline management.

New option for RISC-V Vector performance simulation

0 implied HN points • 20 Mar 22
  1. Rivos Inc is extending GEM5 to support RVV in the RISC-V race.
  2. More information is available on the gem5-dev mailing list and Rivos's GitHub page.
  3. The port by Rivos Inc is not directly related to other efforts but can still be followed based on the author's initial article.

Introduction to polynomial approximation (WiP)

0 implied HN points • 21 Nov 20
  1. The goal is to find the best polynomial to approximate a given function within an interval by minimizing error.
  2. The Remez algorithm solves linear systems to find coefficients for a minmax approximation polynomial.
  3. During iteration, the lower bound for approximation error is the minimum of the differences between the polynomial and the function.