The hottest Computer Architecture Substack posts right now

And their main takeaways
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Compatibility and Fragmentation in the AI Era

The Chip Letter • 5241 implied HN points • 11 Mar 26
🕹 Technology Computer Architecture
  1. New hardware architectures keep creating compatibility headaches because different instruction sets and designs make it hard to run the same software across machines.
  2. High-level languages, intermediate representations, and architecture strategies that enforce compatibility (like IBM’s System/360) have historically reduced that burden by making software more portable and lowering support costs.
  3. A new wave of novel architectures plus AI promises more fragmentation but also new AI-driven ways to bridge differences, and how the industry manages that will shape who wins and loses.

Nvidia's Groq Plot Thickens

The Chip Letter • 6334 implied HN points • 04 Mar 26
🕹 Technology Computer Architecture
  1. Nvidia is quickly integrating Groq’s low-latency processor technology and team and is expected to unveil a Groq-derived inference chip at GTC.
  2. Groq’s dataflow architecture plus years of compiler work could deliver extremely fast, low-latency inference if Nvidia combines it with its wider IP and engineering.
  3. If Nvidia pulls this off it could narrow the field of inference accelerators and become a major, potentially game-changing shift in computer architecture for AI.

Intel's Larabee Legacy

The Chip Letter • 7426 implied HN points • 24 Jan 26
🕹 Technology Computer Architecture
  1. Larrabee was Intel's attempt to build a GPU by extending x86, but the design proved uncompetitive and the project was cancelled.
  2. The project added large new vector instructions (LRBni / 512-bit vectors) and architectural baggage that increased complexity without producing a viable graphics product.
  3. Larrabee's failure left Intel without a competitive discrete GPU, costing time and money and contributing to long-term cultural and strategic problems that weakened its position in AI and graphics markets.

TPU Mania

The Chip Letter • 18128 implied HN points • 13 Dec 25
🕹 Technology Computer Architecture
  1. Google’s TPU program is the result of a long, steady effort dating back to 2013, evolving from a simple TPU v1 co‑processor into massive cloud AI supercomputers using systolic-array ideas and iterative hardware improvements up to TPU v7.
  2. Google’s control of the full stack, huge resources, and datacenter expertise give TPUs a strong practical advantage, but selling TPUs externally creates strategic trade‑offs and means customers should avoid becoming fully dependent on a single vendor.
  3. The TPU vs GPU contest is still open: architectural strengths matter, but ecosystem, software, and execution will likely decide market share, and we should expect convergence rather than one clear winner.

Jensen Groks Groq

The Chip Letter • 5241 implied HN points • 31 Dec 25
🕹 Technology Computer Architecture
  1. Groq’s LPUs deliver much faster, low‑latency AI inference by storing model parameters in on‑chip SRAM and linking many chips together, avoiding reliance on scarce HBM.
  2. Nvidia struck a non‑exclusive licence and talent deal that moves most Groq employees to Nvidia and pays shareholders, while Groq remains operating with a new CEO and GroqCloud continuing.
  3. Bringing Groq’s processors into Nvidia’s AI platform could let real‑time, high‑speed inference scale broadly and shift the economics and architecture of AI inference.
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Emulating future RISC-V Vector extensions

Fprox’s Substack • 145 implied HN points • 08 Mar 26
🕹 Technology Computer Architecture
  1. You can emulate proposed RISC‑V Vector extensions by translating them into RVV 1.0 intrinsics, so programs using new instructions can run on existing RVV1.0 hardware without compiler or hardware support for the new ops.
  2. The generated emulation is functional and easy to run but not optimal: the code is verbose and much slower than a dedicated hardware implementation, though it still lets you measure real performance and iterate on designs.
  3. The tool is Python‑driven and open source, already supports several draft extensions, and is useful for extension designers and early application developers to prototype and test features before toolchain or hardware support exists.

The Sequence Opinion #819: How AI Chips are Made?

TheSequence • 238 implied HN points • 05 Mar 26
🕹 Technology Computer Architecture
  1. Hardware drives modern deep learning: algorithms explain maybe 40% of progress and the rest comes from the compute, memory, and system-level engineering that makes training and inference practical.
  2. GPUs were a lucky fit for neural nets because their high arithmetic density matched the workload, but custom AI chips are needed to close remaining gaps by optimizing dataflow, precision, and memory access.
  3. Designing an AI chip is a layered engineering craft from architecture to physics and tape‑out, involving RTL/Verilog work, hardware–software co‑design, and careful trade‑offs across performance, power, and manufacturability.

MIPS

The Chip Letter • 10920 implied HN points • 19 Jul 25
🕹 Technology Computer Architecture
  1. MIPS was once a leading computer architecture that powered many devices, but it recently lost its relevance as it shifted away from its original designs.
  2. Despite its decline, MIPS had a notable impact on technology history, including being part of significant products like the Nintendo 64 and contributing to the development of early RISC designs.
  3. Today, while MIPS the architecture isn't prominent anymore, it still exists in some older devices and has influenced technology in places like China.

Beyond the Instruction Stream

More Than Moore • 467 implied HN points • 03 Feb 26
🕹 Technology Computer Architecture
  1. They use a dataflow architecture that runs the compiler's intermediate graph directly instead of a traditional instruction stream, so pipelines stay full and ALUs can execute whole loops every cycle for much higher effective throughput.
  2. Memory is handled by many small, localized MMU-like units plus runtime telemetry that adapts allocations to reduce false sharing, enabling an order-of-magnitude more outstanding memory requests and very high HBM utilization even on irregular workloads like GUPS.
  3. Their go-to-market and tooling are HPC-first while supporting common parallel models (OpenMP, CUDA, Kokkos) with a "bring your own code" approach, hardware-accelerated low-overhead kernel reconfiguration, and chiplet/RDMA-style scaling, with AI-specialized designs planned later.

Software Machine Tools

Bzogramming • 61 implied HN points • 03 Mar 26
🕹 Technology Computer Architecture
  1. There is no universal machine tool: every manufacturing process has hard trade-offs in cost, speed, materials, and geometry, and even hypothetical atom-by-atom assemblers would face stability, energy, and material limits.
  2. In software, theoretical universality (Turing-completeness) doesn’t imply practical usefulness—different paradigms like programming languages, neural networks, and superoptimizers are distinct "software machine tools" with very different real-world strengths.
  3. Big opportunities lie in alternative software tools and analyses—verification-driven code synthesis, superoptimizers, compact magic-constant solutions, better static analysis, and more visual/geometric tooling can solve hard problems more efficiently than brute-force code or giant models.

RISC-V Vector Is Expanding

Fprox’s Substack • 269 implied HN points • 25 Jan 26
🕹 Technology Computer Architecture
  1. Zvabd adds vector integer absolute-value and absolute-difference instructions plus widened-accumulate variants, targeting DSP use and keeping some ops limited to 8/16-bit to reduce hardware cost.
  2. Zvzip provides vzip, vunzip (even/odd), and vpair instructions to interleave and extract paired elements more directly than emulating with vcompress, and these new ops support optional masking.
  3. Zvdot4a8i defines 4-element 8-bit dot-product vector ops (vector-vector and vector-scalar) that multiply and accumulate 4×8-bit groups into 32-bit results, paving the way for faster matrix-style computations.

An Interview with Dr. Krste Asanović

More Than Moore • 280 implied HN points • 15 Jan 26
🕹 Technology Computer Architecture
  1. RISC-V was designed as a simple, open, and modular ISA so researchers and companies can get a minimal base running quickly while adding custom extensions as needed. This lets hardware scale from tiny embedded devices to high-performance servers without forcing unnecessary features on every design.
  2. Real-world silicon and developer boards were crucial to turning academic work into a growing industry, which led to SiFive and many commercial design wins; building reusable IP for many customers is a different challenge than making a single research chip. Getting chips into developers' hands speeds software porting and ecosystem growth.
  3. A standards body and formal Profiles like RVA23 are essential to keep the ecosystem interoperable while still allowing customization, and extensions like the vector and upcoming matrix features target AI workloads. Completing compliance test suites and coordinating vendors are the next big steps to prevent fragmentation and ensure reliable implementations.

Motorola's 6809 : The Best 8-Bit?

The Chip Letter • 17 HN points • 03 Mar 24
🕹 Technology Computer Architecture
  1. Motorola's 6809 microprocessor series evolved to become a major player in the 8-bit era, competing with the likes of Intel and Zilog.
  2. The architecture of the 6809 was designed with 'source code' compatibility with the 6800, allowing programs written in 6800 assembly language to run, but with changes in machine code.
  3. Despite its advancements, the 6809 faced limitations due to the rise of more advanced processors like the 68000, leading to it being seen as an evolutionary rather than revolutionary design.

[V]ery [L]ong [I]ncoherent [W]riteup

Irrational Analysis • 1 HN point • 24 Feb 24
🕹 Technology Computer Architecture
  1. VLIW architectures are unique computer architectures with benefits like low power consumption, low latency, and area efficiency, but they come with a significant challenge for compilers, often requiring manual assembly coding by experts.
  2. Historically, VLIW architectures have a long and colorful history dating back to the early 1980s, including examples like Intel Itanium, Movidius/Intel, Xilinx/AMD, Qualcomm Hexagon, Google TPU, and Texas Instruments VelociTI, each with varying degrees of success and challenges.
  3. Groq, a company leveraging VLIW architecture, demonstrates the ongoing struggle with VLIW compilers, as highlighted through their efforts to optimize performance for a specific model, showcasing the complexities and limitations associated with 144-wide VLIW architecture.

Khải Trần: công nghệ chip máy tính tiến về đâu?

Thái | Hacker | Kỹ sư tin tặc • 19 implied HN points • 19 Sep 18
🕹 Technology Computer Architecture
  1. The history of computer chip technology evolution highlights the shift from vacuum tubes to transistors leading to higher performance and faster clock speeds.
  2. The era of Moore's Law brought about significant advancements in chip design by increasing the number of transistors and optimizing instruction execution.
  3. With the end of Moore's Law approaching, the future of chip technology may involve domain-specific chips tailored for specific tasks, like deep learning, to overcome physical limitations and energy consumption challenges.

Lập trình máy kỳ dị

Thái | Hacker | Kỹ sư tin tặc • 19 implied HN points • 11 Feb 14
🕹 Technology Computer Architecture
  1. Microcorruption game is a fun way to practice reverse engineering and memory exploitation skills, with varying levels of difficulty to learn from and enjoy.
  2. Playing Microcorruption requires understanding computer structure, memory organization, and different types of vulnerabilities and attacks commonly used in software exploitation.
  3. Reprogramming a running program involves complexities like controlling program state, manipulating memory, and executing desired commands, showcasing the intriguing world of software exploitation.

The Relentless Pursuit of Moore’s Law

Bits and Bytes • 1 HN point • 24 Sep 23
🕹 Technology Computer Architecture
  1. Innovations in the pursuit of Moore's Law evolved individually until high-volume semiconductor manufacturing adopted them.
  2. Advancements in transistor density and computer design followed an S-curve pattern with periods of rapid progress followed by diminishing returns.
  3. Architectural innovations, like wider instruction widths and core-level parallelism, drove the evolution of computers with each 10X increase in transistor count.

Merge Sort And It's Early History

Luminotes • 0 implied HN points • 21 Apr 23
🕹 Technology Computer Architecture
  1. Merge sort has an interesting early history related to computer architecture and assembly language
  2. The original merge sort program was designed to test programming languages and computer architecture
  3. Understanding the context behind Neumann's first program is essential to grasping the code and its significance