SemiAnalysis • 9799 implied HN points • 13 Jan 26
- 3D NAND makers are still squeezing more bits by adding layers and decks; SK Hynix’s 321-layer V9 boosts capacity a lot and its multi-site 5-bits-per-cell idea shows big logical-density potential, but these tricks add serious process complexity and cost.
- Metals are changing to beat copper limits: Samsung is using molybdenum to cut wordline resistance in NAND, and ruthenium is emerging for ultra-fine interconnects with textured ALD that can greatly lower line resistance at tiny pitches.
- Two-dimensional materials keep promise for sub‑10 nm logic because they reduce source‑to‑drain tunneling, but real-world barriers—wafer‑scale integration, low‑bias contacts (especially p‑type), variability, doping methods, and modeling—still need to be solved before they become manufacturable.