Fproxβs Substack β’ 2 HN points β’ 14 Apr 23
- The post describes how to extend the RISC-V ISA simulator Spike to implement a new instruction for vector AES-128 encryption.
- It covers steps like adding the new opcode in riscv-opcodes, declaring the new instruction in riscv-isa-sim, and testing the program.
- The process involves modifying opcode header files, updating the simulator, and building a test program to implement and verify the new instruction.