SemiAnalysis ⢠11314 implied HN points ⢠12 Mar 26
- Advanced 3nm (TSMC N3) wafer capacity is deeply constrained because most leading AI accelerators are moving to N3, so compute deployments are bottlenecked and TSMC is prioritizing AI customers which may push others to diversify to Samsung or Intel.
- Memory is the next big bottleneck: HBM demand is surging, it consumes far more wafer capacity per bit than commodity DRAM, and higher HBM pin-speed requirements plus rising DRAM prices mean suppliers will struggle to meet accelerator needs without charging premiums.
- A small release valve exists if smartphone demand falls (freeing some N3 wafers) and CoWoS packaging constraints are easing, but memory, datacenter power, and packaging limits mean hyperscalersā higher capex wonāt immediately solve the compute shortage.